The current overriding limitation in the operating speed of all-electronic processors is primarily due to the problems associated with physical wiring. For example, all-electronics processors use physical wiring, such as co-planar metallic strip lines that suffer from an impedance mismatch with electronic logic devices. Such an impedance mismatch leads to a large power consumption as well as a low operating speed. Furthermore, the communication speed between electronic elements is critically dependent on the characteristic R-C time constant of the interconnecting metallic wires.
While alternative interconnection architectures have improved the operating speeds of some processor systems, they have not been completely satisfactory in effectively reducing the R-C time constant when the dimensions of the devices are further reduced. This can be best understood by realizing that while the parasitic capacitance, C, decreases with size, the resistance, R, does not, but rather increases, maintaining the R-C time constant relatively fixed.
Also problematic is the noise associated with the utilization of physical wiring. Generally, whenever the signal through a loop of strip-line connections changes, a voltage spike is generated. For digital systems, costly and complex error reduction techniques must be employed to compensate for the noise in order to achieve the desired bit-error rate. Additionally, communication among the hundreds or even thousands of electronic logic devices found on VLSI integrated circuits is generally serial, resulting in the classic Von Neumann bottleneck problem.
One solution to the impedance mismatch and Von Neumann bottleneck problems is the implementation of optoelectronic interconnects. See, for example, Goodman, J. W., et al., Appl. Opt., Vol. 27, pp. 1742 (1988), and Kostuk, R. K., et al., App. Opt., Vol. 24 (1985), which are incorporated herein by reference. Optoelectronic interconnects act as quantum impedance matching elements that use optical beams for establishing interconnects or communication paths between electronic elements in order to avoid mismatching and bottlenecking. Unlike physical wiring, these impedance matching elements, such as lasers and photo-receivers, convert electrons to photons and then photons back to electrons in establishing the interconnects. Advantageously, optical beams do not strongly interact with each other, thereby also substantially improving the noise immunity. Moreover, for optical interconnects, the power and bandwidth requirements do not depend on distance as do physical wires.
Considerable efforts concerning the architecture of such optoelectronic interconnects have been expended. For instance, recently proposed architectures include the use of two-dimensional arrays of surface emitting laser diodes and detector arrays integrated on a single semiconductor substrate as set forth, for example, in J. L. Jewell et al., SPIE International Conference on Advances in Interconnection and Packaging, Vol. 1389, pp. 401-407 (1990); J. Jahns, SPIE International Conference on Advances in Interconnection and Packaging, Vol. 1389, pp. 523-526 (1990); A. G. Dickinson et al., SPIE International Conference on Advances in Interconnection and Packaging, Vol. 1389, pp. 503-514 (1990); H. D. Hendricks et al., IEEE Proceedings--1989 Southeastcon, Session 12B5, pp. 1132-1139; and P. K. L. Yu et al., SPIE Optoelectronic Signal Processing for Phased-Array Antennas, Vol. 886, pp. 1-11 (1988), all of which are incorporated herein by reference.
A problem that remains in the prior art is to provide an interconnection architecture which (1) utilizes high speed, efficient optoelectronic integrated circuit (OEIC) transmitters/receivers, (2) utilizes an OEIC interconnect technology compatible with three-dimensional hybrid opto electronics signal processing systems, and (3) is suitable for fabrication and capable of rigid intrastack optical interconnect alignment.